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Ordering number:ENN3802A
CMOS IC
LC7233
Single-Chip PLL and Microcontroller with LCD Driver
Overview
The LC7233 is a single-chip microcontroller that incorporates a phase-locked loop (PLL), which can operate up to 150MHz, and a liquid-crystal display (LCD) driver, making it ideal for digital tuners. It has a large number of input/ output ports and a frequency measurement circuit. The LC7233 freatures on-chip RAM and ROM, a programmable high-speed divider, a 6-bit analog-to-digital converter and a low-voltage detection reset circuit. The LC7233 operates from a single 5V supply and is available in 64-pin QIPs.
Package Dimensions
unit:mm 3159-QIP64E
[LC7233]
17.2 1.0 1.6 1.0 48 49 32 0.8 14.0 0.35 33 1.6 1.0 0.15
17.2
14.0 0.8
Features
* 150 MHz phase-locked loop. * LCD driver. * 6-bit analog-to-digital converter. * Two 8-bit PWM digital-to-analog converters. * Two 4-bit input ports. * Two 4-bit input/output ports. * 6-bit keypad matrix scan output. * 2-bit open-drain high-voltage output. * 23 mask-selectable output drivers. * 20-bit universal counter. * 4096 x 16-bit program ROM (000H to FFFH user-addressable memory). * 256 x 4-bit data RAM. * Low-voltage detection reset circuit. * Programmable high-speed divider. * Single-word instructions. * Four-level stack. * PLL-unlocked flip-flop. * Timer flip-flop. * Programmable watchdog interrupt address. * Standby mode. * CPU operates down to 3.5V, with data retention down to 1.3V. * Single 5V supply. * 64-pin QIP.
17 1.0 1 16 3.0max 0.8 64 0.1 2.7
15.6
SANYO : QIP64E
Pin Assignment
Top view
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
71901TN (KT)/6291JN/1201JN No.3802-1/12
LC7233
Block Diagram
No.3802-2/12
LC7233
Pin Description
Number 1 Name XIN Crystal oscillator connections 64 2 63 XOUT TEST2 TEST1 Equivalent circuit Description
Test pins
3 to 6
PG3 to PG0
Input port G
7, 8
PH1, PH0
Output port H
9 to 12
PF3 to PF0
Input/output port F
13 to 16
PE3 to PE0
Input/output port E
17, 18
PC1, PC0
Output port C
19 to 22
PB3 to PB0
Output port B
23 to 26
PA3 to PA0
Input port A
27 to 49
S23 to S1
LCD segment outputs
Continued on next page.
No.3802-3/12
LC7233
Continued from preceding page.
Number Name Equivalent circuit Description
50, 51
COM2, COM1
LCD common driver outputs
52
HOLD
Hold-mode control input
55
SNS
Power-fail detect
53
ADI
A/D converter input
54
HCTR
Univarsal counter input
56
VDD
5V supply
57
FMIN
FM VCO input
58
AMIN
AM VCO input
59
VSS
Ground
60
EO
Phase comparator output
61
AIN
Analog input
62
AOUT
Analog output
No.3802-4/12
LC7233 Specifications
Absolute Maximum Ratings
Parameter Supply voltage Port G, HOLD, ADI and SNS input voltage Input voltage (other inputs) Port H and AOUT output voltage Output voltage (all other outputs) Port H output current Ports E and F output current Porst B and C output current AOUT output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 IOUT3 IOUT4 Pd max Topr Tstg Conditions Ratings - 0.3 to +6.5 - 0.3 to +13
- 0.3 to VDD+0.3 - 0.3 to +15 - 0.3 to VDD+0.3 0 to 5 0 to 3 0 to 1 0 to 2
Unit V V V V V mA mA mA mA mW C C
400 - 40 to +85 - 45 to +125
Reommended Operating Conditions at Ta = 25C
Parameter Supply voltage Supply voltage range (PLL and CPU) Supply voltage range (CPU) Supply voltage range for data retention Symbol VDD VDD1 VDD2 VDD3 Conditions Ratings 5 4.5 to 5.5 3.5 to 5.5 1.3 to 5.5 Unit V V V V
Electrical Characteristics at Ta = -40 to +85C, VDD = 3.5 to 5.5V, unless otherwise noted
Parameter Port G high-level input voltage SNS high-level input voltage Port A high-level input voltage Ports E and F high-level input voltage HOLD high-level input voltage Port G low-level input voltage HOLD low-level input voltage SNS low-level input voltage Port A low-level input voltage Ports E and F low-level input voltage XIN input frequency FMIN input frequency AMIN input frequency (low range) AMIN input frequency (high range) HCTR input frequency XIN rms input amplitude FMIN rms input amplitude AMIN rms input amplitude HCTR rms input amplitude ADI input voltage range SNS reject pulsewidth Standby threshold voltage HOLD, ADI, SNS and port G high-level input current Ports A, E and F high-level input current XIN high-level input current FMIN, AMIN and HCTR high-level input current Port A high-level input current AIN high-level input current HOLD, ADI, SNS and port G low-level input current Ports A, E and F low-level input current Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIL1 VIL2 VIL3 VIL4 VIL5 fIN1 fIN2 fIN3 fIN4 fIN5 VIN1 VIN2 VIN3 VIN4 VIN5 Prej VDET IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 VIN=5.5V Ports E and F are high impedance, Port A has no RPD, VIN=VDD VIN=VDD=5.0V VIN=VDD=5.0V VIN=VDD=5.0V, Port A has RPD VIN=VDD VIN=VSS Ports E and F are high impedance, Port A has no RPD, VIN=VSS 2 4 5 10 50 0.01 10.0 3.0 3.0 2.7 3.0 VIN=0.5 to 1.5V VIN=0.1 to 1.5V, VDD=4.5 to 5.5V VIN=0.15 to 1.5V, VDD=4.5 to 5.5V VIN=0.1 to 1.5V, VDD=4.5 to 5.5V VIN=0.1 to 1.5V, VDD=4.5 to 5.5V VIN=0.1 to 1.5V, VDD=4.5 to 5.5V Conditions Ratings min 0.7VDD 2.5 0.6VDD 0.7VDD 0.8VDD 0 0 0 0 0 4.0 10 10 0.5 2.0 0.4 0.5 0.1 0.1 0.1 0 4.5 typ max 8.0 8.0 VDD VDD 8.0 0.3VDD 0.4VDD 1.3 0.2VDD 0.3VDD 5.0 130 150 10 40 12 1.5 1.5 1.5 1.5 VDD 50 3.3 3.0 3.0 15 30 Unit V V V V V V V V V V MHz MHz MHz MHz MHz V V V V V s V A A A A A nA A A
Continued on next page. No.3802-5/12
LC7233
Continued from preceding page.
Parameter XIN low-level input current FMIN, AMIN and HCTR low-level input current AIN low-level input current Port A input voltage Port A pull-down resistance EO output leakage current Ports B, C, E and F output leakage current Port H output leakage current AOUT output leakage current EO output leakage current Ports B, C, E and F output leakage current Ports B and C high-level output voltage Ports E and F high-level output voltage EO high-level output voltage XOUT high-level output voltage S1 to S23 high-level output voltage COM1 and COM2 high-level output voltage Ports B and C low-level output voltage Ports E and F low-level output voltage EO low-level output voltage XOUT low-level output voltage S1 to S23 low-level output voltage AOUT low-level output voltage COM1 and COM2 low-level output voltage Port H low-level output voltage COM1 and COM2 mid-level output voltage A/D converter error Supply current Hold-mode supply current Symbol IIL3 IIL4 IIL5 VIF RPD IOFFH1 IOFFH2 IOFFH3 IOFFH4 IOFFL1 IOFFL2 VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 VOL7 VOL8 VM1 IDD1 IDD2 VIN=VSS VIN=VSS VIN=VSS Port A is high impedance. VDD=5V VO=VDD VO=VDD VO=13V VO=13V VO=VSS VO=VSS IO=1 mA IO=1 mA IO=500A IO=200A IO=- 0.1mA IO=25A IO=50A IO=1 mA IO=500A IO=200A IO=0.1mA IO=5mA, AIN=1.3V IO=25A IO=5mA VDD=5V, IO=20A VDD=4.5 to 5.5V fin=130MHz, VDD=4.5 to 5.5V PLL halted, tcyc=2.67s PLL halted, tcyc=13.33s, VDD=3.5 to 5.5V PLL halted, tcyc=40.00s, VDD=3.5 to 5.5V Standby-mode supply current IDD3 VDD=5.5V, oscillator halted, Ta=25C VDD=5.5V, oscillator halted, Ta=25C 0.3 0.75 2.0
- 1/2
VDD- 1.0 VDD- 1.0 VDD- 1.0 VDD- 1.0
VDD- 0.75
Conditions
Ratings min 2 4 typ 5 10 0.01
75
max
15
Unit A A nA V k nA A A A A A V V V V V V
30
10.0
0.05VDD
100 0.01
200 10.0
3.0
5.0 1.0 0.01 10.0
3.0
VDD- 2.0 VDD- 1.0 VDD- 0.5
0.5
1.0
2.0 1.0 1.0 1.0 1.0 0.5
V V V V V V V V V lsb mA mA
0.5 2.5 15 1.5 1.0 0.7
0.75
2.0
3.0
+1/2 20
5 1
A
Test Circuits
Hold Mode
Notes 1. Ports E and F are selected as output ports. 2. Ports A to H, S1 to S23, COM1 and COM2 are open.
No.3802-6/12
LC7233
Standby Mode
Note Ports A to H, S1 to S23, COM1 and COM2 are open.
Functional Description
LCD Driver The LC7233 can drive LCD segments. The LCP and LCD instructions transfer data to the LCD outputs. The LCD instruction transfers data directly to the LCD outputs. The LCP instruction converts data to 7-segment format before transfer to the outputs. S1 to S23 are the driver outputs. The LCD frame rate is 100Hz with a 50% duty cycle. After reset or power-up, a blank signal is present on all outputs. In standby mode, all outputs are LOW. They can be used as general-purpose outputs if the appropriate mask option is selected. COM1 and COM2 are the LCD common driver outputs. Output drive is 50% duty with 50% bias. Upon reset or after power-up, the normal drive signals are present on these outputs. In standby mode, all outputs are LOW. Frequency Counter Frequency measurement is performed at the HCTR input by the 20-bit universal counter. The input frequency range is 0.4 to 12MHz, which is used for measuring AM and FM IF frequencies. Capacitive coupling should be used. Phase-Locked Loop The FMIN or AMIN input signal is divided down by a programmable divider, and then compared with the crystal frequency, which is also divided down using 14 selectable ratios. The phase difference between the two signals is measured using a phase detector and output on EO. FMIN is the input pin for the FM VCO input signal. The input frequency range is 10 to 130MHz. Capacitive coupling should be used. AMIN is the AM VCO input. The bandwidth is adjustable in two ranges by using the PLL instruction-HIGH (2 to 40MHz) for the SW band, and LOW (0.5 to 10MHz), for the LW and MW bands. Capacitive coupling should be used. Input/Output Ports Port A This input port has a low switching threshold, which is used for keypad matrix inputs. Pull-down resistors for all pins are available as a mask option. Note that either all or none of the pins should have pull-down resistors. In standby mode, inputs are ignored. Ports B and C These output ports have unbalanced CMOS outputs which are used as keypad matrix scan outputs. Upon reset, outputs are set LOW, and in standby mode, outputs are high impedance. The outputs can be short-circuited. Port E The transfer direction of this input/output port is selected automatically under software control. When an input instruction (IN, TPT, or TPF) is executed, port E is configured for input operation, and an output instruction (OUT, SPB or RPB), for output operation. Upon reset, all pins become inputs. In standby mode, the output drivers are high impedance and the input signals are ignored. All bits should either be inputs or outputs.
No.3802-7/12
LC7233
Port F The transfer direction of this input/output port is selected by the FPC instruction. Each pin of this port can be set independently to be an input or an output. Upon reset, all pins become inputs. In standby mode, the output drivers are high impedance and the input signals are ignored. Port G This is an input port only. In standby mode, inputs are ignored. Port H These output ports are high-voltage, n-channel open-drain drivers, which are used for switching power supplies. Upon reset and in standby mode, outputs are high impedance. Port H can also be configured as the output of DACI and DAC2. A/D Converter The A/D converter is a 6-bit successive approximation type. The conversion cycle time is 1.28 ms. Full-scale output data is 3FH for an input of VDD x (63/96). Power-Fail Detection When connected to the supply, SNS is used as a power-fail detector. SNS can also be used as a standard input port. Crystal Oscillator The master crystal oscillator, which has a feedback resistor on-chip, requires only the connection of a 4.5 MHz crystal. Low-Power Modes Hold Mode When the hold-mode control pin, HOLD, is driven LOW and the HOLDEN (hold enable) flip-flop has previously been set by an SS instruction, the LC7233 enters hold mode. HOLD has a high-voltage input (VIH(max) = 8.0V) which can be connected directly to the power supply. Standby Mode When the LC7233 is in hold mode and HOLD is LOW, standby mode can be set by the CKSTP instruction. Test Pins Two device test pins are provided-TEST1 and TEST2. These should either be tied to VSS or left open.
Instruction Set
ADDR b B C DH DL I M N Pn r Rn () ( )n Program memory address [12 bits] Borrow Bank number [2 bits] Carry Data memory address high-order bits (row address) [2 bits] Data memory address low-order bits (column address) [4 bits] Immediate data [4 bits] Data memory address Bit position [4 bits] Port number [4 bits] General register (Bank 00H to 0FH) Register number [4 bits] Contents of register or memory Contents of bit N of register or memory
No.3802-8/12
Mnemonic D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Operand Notation Description Skip condition Add instructions 0 0 0 0 0 0 0 0 Subtract instructions 1 1 1 1 1 1 1 1 Compare instructions 0 0 1 1 1 1 1 DH DL 1 0 1 DH DL 0 1 1 DH DL 0 0 1 DH DL Rn Rn I I
Compares the contents of r and M and skips if they are equal. Compares the contents of r and M and skips if r is greater than or equal to M.
1st
2nd
Operation
Instruction format
D15 D14
AD 0 0 0 1 1 1 1 1 1 DH DL I M (M) + I + C, skip if carry 1 0 DH DL I M (M) + I + C 0 1 DH DL I M (M) + I, skip if carry 0 0 DH DL I M (M) + I 1 1 DH DL Rn r (r) + (M) + C, skip if carry
Adds the contents of M to the contents of r and C and stores the result in r. Skips if a carry is generated. Adds the immediate data to the contents of M and stores the result in M. Adds the immediate data to the contents of M and stores the result in M. Skips if a carry is generated. Adds the immediate data to the contents of M and C and stores the result in M. Adds the immediate data to the contents of M and C and stores the result in M. Skips if a carry is generated.
r 0 1 0 DH DL Rn r (r) + (M) + C
Adds the contents of M to the contents of r and C and stores the result in r.
M 1 DH DL Rn r (r) + (M), skip if carry
Adds the contents of M to the contents of r and stores the result in r. Skips if a carry is generated.
Add M to r.
0
1
0
0
0
DH
DL
Rn
r (r) + (M)
Adds the contents of M to the contents of r and stores the result in r.
ADS
r
M
Add M to r and skip if carry.
0
1
Carry
AC
r
M
Add M to r with carry.
0
1
ACS
r
M
Add M to r with carry and skip if carry.
0
1
Carry
AI
M
I
Add I to M.
0
1
AIS
M
I
Add I to M and skip if carry.
0
1
Carry
AIC
M
I
Add I to M with carry.
0
1
AICS
M
I
Add I to M with carry and skip if carry.
0
1
Carry
SU 0 0 0 1 1 1 1 1 1 DH DL I 1 0 DH DL I 0 1 DH DL I 0 0 DH DL I M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow 1 1 DH DL Rn r (r) - (M) - b, skip if borrow 1 0 DH DL Rn r (r) - (M) - b 0 1 DH DL Rn r (r) - (M), skip if borrow
r
M
Subtract M from r.
0
1
0
0
0
DH
DL
Rn
r (r) - (M)
Subtracts the contents of M from the contents of r and stores the result in r. Subtracts the contents of M from the contents of r and stores the result in r. Skips if a borrow is generated.
SUS
r
M
Subtract M from r and skip if borrow.
0
1
Borrow
SB
r
M
0
1
LC7233
SBS
r
M
Subtract M from r with borrow. Subtract M from r with borrow and skip if borrow.
0
1
Borrow
SI
M
I
Subtract I from M.
0
1
Subtracts the contents of M from the contents of r with borrow and stores the result in r. Subtracts the contents of M from the contents of r with borrow and stores the result in r. Skips if a borrow is generated. Subtracts the immediate data from the contents of M and stores the result in M. Subtracts the immediate data from the contents of M and stores the result in M. Skips if a borrow is generated.
SIS
M
I
Subtract I from M and skip if borrow.
0
1
Borrow
SIB
M
I
0
1
SIBS
M
I
Subtract I from M with borrow. Subtract I from M with borrow and skip if borrow.
0
1
Subtracts the immediate data from the contents of M with borrow and stores the result in M. Subtracts the immediate data from the contents of M with borrow and stores the result in M. Skips if a borrow is generated.
Borrow
SEQ
r
M
Skip if r equals M.
0
0
(r) = (M) (r) (M) - I, skip if zero (M) - I, skip if not borrow (M) I
Compares the immediate data to the contents of M and skips if they are equal. Compares the contents of M with the immediate data and skips if M is greater than or equal to I.
SGE
r
M
Skip if r is greater than or equal to M.
0
0
(r) - (M), skip if zero (r) - (M), skip if not borrow (r) (M)
(M) (M) - I = 0 (M) I
SEQI
M
I
Skip if M equals I.
0
0
SGEI
M
I
Skip if M is greater than or equal to I.
0
0
Continued on next page.
No.3802-9/12
Continued from preceding page.
Instruction format
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mnemonic
Operand Notation Description Skip condition Logic arithmetic instructions 1 1 1 Load and store instructions 0
Moves the contents of M to r. Moves the contents of r to M.
1st
2nd
Operation
D15 D14
AND 1 0 0 0 DH DL Rn r (r) + (M) 1 0 DH DL I M (M) + I
M
I
AND I with M.
0
0
1
0
0
DH
DL
I
M (M) I
OR
M
I
OR I with M.
0
0
EXL
r
M
Exclusive-OR M with r.
0
0
Calculates the logic-AND of the immediate data and the contents of M and stores the result in M. Calculates the logic-OR of the immediate data and the contents of M and stores the result in M. Calculates the logic-XOR of the contents of r and M, and stores the result in r.
LD 0 0 0 0 0 0 Bit test instructions 1 1 Jump and subroutine instructions 1 0 0 Flag test instructions 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 N N N N N 1 0 1 1 0 0 0 0 0 N Skip if timer F/F = 0 Skip if PLL F/F = 0
(Status register 1) N 1
r 0 0 0 1 1 1 1 0 DH DL Rn PLLr PLL DATA 0 1 DH DL I MI 0 0 DH DL1 DL2 1 1 DH DL Rn 1 0 DH DL Rn 0 1 DH DL Rn M (r)
M
Load M into r.
1
0
0
0
0
DH
DL
Rn
r (M)
ST
M
r
Store r in M.
1
0
MVRD
r
M
1
0
MVRS
M
r
Move M to M addressed by Rn. Move M addressed by Rn to M.
1
0
MVSR
M1
M2
Move M to M .
1
0
Moves the contents of M to the address referenced by DH [DH, Rn] (M) and Rn. Moves the contents of the memory location referenced by M [DH, Rn] DH and Rn to M. Moves the contents of memory location 2 to memory [DH. DL1] [DH. DL2] location 1. Moves the immediate data to M. Moves the contents of M to the PLL registers.
MVI
M
I
Move I to M.
1
0
PLL
M
r
Load M to PLL registers.
1
0
TMT 0 1 1 DH DL N skip if M(N) = all 0
M
N
1
0
0
0
1
DH
DL
N
skip if M(N) = all 1
LC7233
TMF
M
N
Test bits of M and skip if ture Test bits of M and skip if false
1
0
Tests the bits of memory location M specified by N. Skips if all bits are logic 1. Tests the bits of memory location M specified by N. Skips if all bits are logic 0.
All bits specified = 1 All bits specified = 0
JMP 0 1 0 1 0 0 0 0 0 0 0 0 0 0 ADDR (12 bits)
ADDR
Jump to address
1
0
1
ADDR (12 bits)
PC ADDR Stack (PC) + 1 PC stack
Jumps to the address specified by ADDR. Jumps to the subroutine specified by ADDR. Returns from a subroutine.
CAL
ADDR
Call subroutine
1
1
RT
Return from subroutine
1
1
TTM
N
Test timer flip-flop
1
1
Tests the timer flip-flop and skips if zero. Tests the PLL-unlocked flip-flop and skips if zero.
Timer F/F = 0 PLL F/F = 0
TUL
N
Test PLL flip-flop
1
1
Status register test and set instructions
Sets the bits of the status register specified by N.
(Status register 1) N 0 Resets the bits of the status register specified by N. Skip if (Status register 2) N = all 1 Skip if (Status register 2) N = all 0
SS
N
Set status register bits
1
1
RS
N
1
1
TST
N
1
1
TSF
N
Reset status register bits Test status register bits and skip if true Test status register bits and skip if false
1
1
Tests the bits of status register 2 specified by N. Skips if all bits are 1. Tests the bits of status register 2 specified by N. Skips if all bits are 0.
All bits specified = 1 All bits specified = 0
Bank select instruction 0 1 0 0 B 0 0 0 0 0 0 0 0
BANK B
BANK
B
Select bank
1
1
Selects one of four memory banks.
No.3802-10/12
Continued on next page.
Continued from preceding page.
Instruction format
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mnemonic
Operand Notation Description Skip condition Input/output instructions 1
Loads the immediate data directly to the LCD driver. Converts the immediate data to 7-segment format using a PLA then transfers it to the LCD driver. Moves the data from input port Pn to M. Moves the contents of memory location M to port Pn. Sets the bits of port Pn, specified by N, to logic 1. Sets the bits of port Pn, specified by N, to logic 0.
1st
2nd
Operation
D15 D14
LCD 1 1 1 1 1 1
Skip if (port (Pn)) N = all 1 Skip if (port (Pn)) N = all 0
M 0 0 0 1 1 1 1 Universal counter instructions 0 0 Miscellaneous instructions 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 I
DACr DAC DATA
I 0 1 1 0 0 1 1 1 1 1 P N 0 1 0 P N 1 0 1 P N
(port (Pn)) N 0
1 1 0 1 0 0 0 P N
(port (Pn)) N 1
1 DH DH DH DL P
(port (Pn)) M
0 DL DL P
M (port (Pn))
0 DIGIT
LCD (DIGIT) PLA M
0
DH
DL
DIGIT
LCD (DIGIT) M
LCP
M
I
Move data to LCD segments. Move 7-segment data to LCD.
1
1
IN
M
Pn
Move port data to M.
1
1
OUT
M
Pn
Move data to port.
1
1
SPB
Pn
N
Set port bits.
1
1
RPB
Pn
N
Reset port bits.
1
1
TPT 1
Pn
N
1
1
TPF
Pn
N
Test bits of port and skip if true. Test bits of port and skip if false.
1
1
Tests the bits of port Pn specified by N. Skips if all bits are logic 1. Tests the bits of port Pn specified by N. Skips if all bits are logic 0.
All bits specified = 1 All bits specified = 0
UCS 0 0 0 1 1 0 0 0 0 I
UCCW2 I
I
Set UCCW1.
0
0
0
0
0
0
1
0
0
0
0
I
UCCW1 I
Sets the universal counter flag 1. Sets the universal counter flag 2.
UCC
I
Set UCCW2.
0
0
FPC 1 0 0 0 1 0 0 0 0 0 0 0 0
Stop clock if HOLD = 0
N
Port F direction control.
0
0
1
0
0
0
0
0
0
0
0
N
FPC latch N
Defines the direction of individual pins of port F. If a bit in the port F direction register is set by FPC, the corresponding pin of port F becomes an output. Stops the processor clock if HOLD = 0 Loads the immediate data to the DAC registers. No operation
CKSTP
Stop clock.
0
0
LC7233
DAC
I
Move data to DAC registers
0
0
NOP
No operation
0
0
No.3802-11/12
LC7233
Mask Option
Parameter Watchdog timer (WDT) Pull-down resistors on port A (the keypad matrix input port) Yes No Yes No 2.67 s Instruction cycle time 13.33 s 40.00 s S1 to S23 configuration LCD driver output port General-purpose output port Options
Development System The LC7223 development environment is shown in figure 1. It uses an LC72EV32 evaluation chip mounted on a TB72EV32 target board and a multifunctional emulator (RE32), which is controlled by a personal computer, to provide full debugging facilities.
Figure 1. Development system
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 2001. Specifications and information herein are subject to change without notice.
PS No.3802-12/12

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